This invention relates to code generators, and more particularly to codes and generators therefor applicable to counting circuitry in avionics channel synthesizers.
In a U.S. Pat. application of Boyd McClaskey and John Smith entitled "Improved Digital Synthesizer," filed concurrently herewith and assigned to the assignee hereof, Ser. No. 543,538, there is described an avionics communication channel synthesizer utilizing a digital phase locked loop employing "pulse swallowing" techniques. In accordance with the scheme set forth therein, a pulse signal from a voltage controlled oscillator is alternately divided by 40 or 41 in response to the fractional MHz component of the channel selected for communication. Thereafter, it is specified, a MHz counter, preset in accordance with the MHz component of the selected channel, further divides the pulse signals by the MHz component (i.e., 118 through 147 MHz including channels allocated to transmit and receive modes), and couples the output signal to a phase/frequency detector for comparison with a reference signal.
In an application of Boyd M. McClaskey filed concurrently herewith and assigned to the assignee hereof, entitled "Fractional Megahertz Counter for Improved Digital Synthesizer" S.N. 543,539, there is set forth a logic scheme and code whereby, in response to the fractional MHz component of the selected channel, the alternate divide by 40/41 counters in the phase locked loop are operated.
In a patent to William M. Wisser, et al., entitled "Avionics Channel Selection Apparatus," Ser. No. 3,879,692 issued Apr. 22, 1975 and assigned to the assignee hereof, there is set forth apparatus whereby the designation of the selected channel is translated into the positioning of rotary wafer switches configured in accordance with predetermined codes.
An aspect not dealt with in detail in the foregoing co-pending applications relates to advantageous embodiment of the MHz counter. Since transmit channels are arrayed between 118 and 135.975 MHz, and receive channels are respectively located 12 MHz above their corresponding transmit channel, an 8 bit code is required to represent the counting process which is between 118 and 147 increments long, depending on the MHz component of the selected channel. The decoding must be carefully selected, however, to correct problems such as the "persistent ones" problem, should they occur. That is, if transmission errors occur whereby the register erroneously contains all logical one signals, it is desirable that the situation be detected and corrected, lest the ones serve to "jam" the counter logic such that no further data would be available to shift through the register. Hence, it is a primary object of the present invention to provide a coding arrangement which avoids the "persistent ones" problem, and a counter including circuitry which generates the specified code.
Furthermore, it is an object that the coding arrangement, and circuitry embodying it, should employ code allocations to the MHz components themselves whereby the rotary wafer switch arrangement set forth in the above captioned patent application of Wisser, et al., conveniently may be utilized to initiate each MHz counting cycle. Finally, after the requisite number of counts, it is desirable that the code entries allocated to the respective receive or transmit modes be detectable by reasonably compact and simple logic, yet be relatively compatible with one another.
Finally, it is an object that all logical apparatus be relatively simple and straightforward in design to minimize quality control and fault detection problems.